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Gallium oxide (β-Ga 2 O 3 ) is becoming a popular material for high power electronic devices due to its wide bandgap and ease of processing. In this work, β-Ga 2 O 3 substrates received various annealing treatments before atomic layer deposition of HfO 2 and subsequent fabrication of metal–oxide–semiconductor (MOS) capacitors. Annealing of β-Ga 2 O 3 with forming gas or nitrogen produced degraded capacitance–voltage (C–V) behavior compared to a β-Ga 2 O 3 control sample with no annealing. A sample annealed with pure oxygen had improved C–V characteristics relative to the control sample, with a higher maximum capacitance and smaller flat-band voltage shift, indicating that oxygen annealing improved the C–V behavior. X-ray photoelectron spectroscopy also suggested a reduction in the oxygen vacancy concentration after O 2 annealing at 450 °C, which supports the improved C–V characteristics and indicates that O 2 annealing of β-Ga 2 O 3 may lead to better MOS device performance. 

Palladium (Pd) electrodes have enabled superior performance in Te‐based devices. Theory predicts strong Fermi level (EF) pinning near the Te valence band, which likely explains the predominantp‐type conduction in Te transistors. The effects of the native TeOx on the contact polarity has not been explored. In this work, X‐ray and ultraviolet photoelectron spectra (XPS and UPS, respectively) reveal the native surface oxide de‐pins the EF between Pd and trigonal Te (t‐Te) and can reduce contact resistance of hole and electron contacts to Te for back end of line‐compatible complementary logic circuits. Atomic hydrogen reduces the native t‐Te oxide below the XPS detection limit, after which, the EF resides near the t‐Te conduction band edge. Therefore, ann‐type band alignment is formed between Pd and t‐Te via an atomic hydrogen treatment. Furthermore, UPS shows the EF is pinned near the t‐Te conduction band edge. XPS indicates the formation of a PdTex intermetallic at the Pdt‐Te interface also affects the electrostatics of the interface. The concentration of PdTex is 40% higher when TeO_xis removed from the t‐Te surface before Pd metallization, likely the root cause of the low (pinned) work function when the native oxide is absent.

 

Sc has been employed as an electron contact to a number of two-dimensional (2D) materials (e.g. MoS₂, black phosphorous) and has enabled, at times, the lowest electron contact resistance. However, the extremely reactive nature of Sc leads to stringent processing requirements and metastable device performance with no true understanding of how to achieve consistent, high-performance Sc contacts. In this work, WSe₂transistors with impressive subthreshold slope (109 mV dec⁻¹) andI_ON/I_OFF(10⁶) are demonstrated without post-metallization processing by depositing Sc contacts in ultra-high vacuum (UHV) at room temperature (RT). The lowest electron Schottky barrier height (SBH) is achieved by mildly oxidizing the WSe₂in situbefore metallization, which minimizes subsequent reactions between Sc and WSe₂. Post metallization anneals in reducing environments (UHV, forming gas) degrade theI_ON/I_OFFby ~10³and increase the subthreshold slope by a factor of 10. X-ray photoelectron spectroscopy indicates the anneals increase the electron SBH by 0.4–0.5 eV and correspondingly convert 100% of the deposited Sc contacts to intermetallic or scandium oxide. Raman spectroscopy and scanning transmission electron microscopy highlight the highly exothermic reactions between Sc and WSe₂, which consume at least one layer RT and at least three layers after the 400 °C anneals. The observed layer consumption necessitates multiple sacrificial WSe₂layers during fabrication. Scanning tunneling microscopy/spectroscopy elucidate the enhanced local density of states below the WSe₂Fermi level around individual Sc atoms in the WSe₂lattice, which directly connects the scandium selenide intermetallic with the unexpectedly large electron SBH. The interface chemistry and structural properties are correlated with Sc–WSe₂transistor and diode performance. The recommended combination of processing conditions and steps is provided to facilitate consistent Sc contacts to WSe₂.